Dr. Ulrich Klostermann: Mastering Lithographic Challenges in current High Volume Manufacturing

invited talk on Thursday July 26, 2012 at 5:0 0 pm in N 5325, N3, 5th floor, speaker is Dr. Ulrich Klostermann


This talk presents some of the hot topics for solving scaling issues at current and upcoming technology nodes. After a brief introduction to lithographic patterning and traditional layout modification to correct for optical interference effects (OPC – optical proximity correction), we focus on current thoughts and solutions as seen by the lithography community and high volume manufacturing industry. We will see real life examples where simulation is employed for co-optimization of mask layout and illumination condition to enhance yield at reduced dimensions (e.g. SMO – Source Mask Optimization techniques for memory cells) or where simulation is used to understand and correct for undesired influences caused by wafer topography.

Finally, we will see that predictive computational lithography is not only beneficial for the advanced technology nodes in semiconductor manufacturing (20 nm or beyond) but also for large dimensions still present e.g. in LCD panel fabrication (above 2 um critical dimensions).

For high volume products (e.g. DRAM, Flash, CPUs) a continuous cost reduction at increased functionality (i.e. more memory and faster speed at cheaper price) is requested by the market.  For semiconductor devices this is mainly ensured by a continuous reduction of the device layout dimensions - the so called scaling. During the electronic device manufacturing process, the layout dimensions must be properly transferred onto the wafer substrate by means of lithography. Hence, lithographic patterning has to cope with ever-smaller dimensions; and even more:  lithography is found to be a key gating factor for successful scaling. The computational simulation and the modeling of the lithographic process have been instrumental to the continuous scaling over the past decade; in fact, computational lithography is currently seen as the main enabler for the next mandatory advancements.

Dr. Ulrich Klostermann is Staff Corporate Application Engineer for Lithographic Simulation at Synopsys, where he is responsible for European and Asian customer support. Part of his work is related to the innovation and the roll-out of new simulation methods and flows to address critical lithographic issues.

Dr. Klostermann received a doctoral degree in physics from University of Regensburg in 2001, with a thesis on submicron sized magnetic tunnel junctions (MRAM).  Subsequently, he worked on various MRAM R&D topics for the MRAM Development Alliance IBM/Infineon (Hopewell Junction, New York, 2001-2003) and for IBM/Infineon joint venture Altis Semiconductor (Paris, France, 2003-2006). From 2006-2008 he joined the Technology Innovation Department of Qimonda (Neubiberg, Germany), where he was lead expert for MRAM activities. Since 2008, Ulrich Klostermann joined the EDA industry and started at SYNOPSYS GmbH located in Aschheim/Dornach, Germany.