Phase Locked Loop / Clocked Circuits
Lecturer (assistant) |
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Number | 0000000205 |
Type | |
Duration | 3 SWS |
Term | Wintersemester 2023/24 |
Language of instruction | English |
Position within curricula | See TUMonline |
Dates | See TUMonline |
Admission information
Objectives
In a written final exam (60 min), students will demonstrate their insight into the basic concepts and structures of PLL and Clocked Circuits, as well as their ability to apply them in practical design problems.
Description
a) Principle of clocked circuits
b) Frequency versus time domain
c) Classes of oscillators
d) Clock generation
e) Clock multiplication
f) PLL
i. Modelling of transfer functions
ii. Noise analysis
iii. System considerations
iv. Digital & Analog
v. Integer & Fractional
g) Phase control
i. DLL
ii. Interpolators"
Prerequisites
Solid-State and Semiconductor Device Physics, Analog and Mixed-Signal Electronics
Teaching and learning methods
Upon successful completion of the module, students are able to understand the concepts and structures of PLL and Clocked Circuits. The students have an insight into the typical non-idealities of such circuits. Students are able to describe basic interaction between circuit specifications and the sizing and structure of the circuit.
Examination
In a written final exam (60 min), students will demonstrate their insight into the basic concepts and structures of PLL and Clocked Circuits, as well as their ability to apply them in practical design problems.
Recommended literature
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