Measuring at the (b)leading edge
Benjamin Krüger, Keysight Technologies, Boeblingen, Tuesday 30.04.24 at 4 PM
Abstract:
Measuring at the (b)leading edge: an introduction to high-speed arbitrary waveform generators, their usage in the development of today’s fastest communication systems, and an overview on the challenges in measuring at physical limits.
CMOS Micro Electrode Arrays for Neural Tissue Recording and Stimulation with high Spatiotemporal Resolution: A Topical Review
Roland Thewes, TU Berlin, Chair of Sensor and Actuator Systems, Tuesday 16.04.24 at 4 PM
Abstract:
Ex-vivo Micro Electrode Arrays (MEAs) have become a technical standard tool to record nerve signals from neural tissue and to stimulate the tissue. MEA technology had begun with passive devices decades ago – i.e. with chips only having the sensor sites on board – the requirement for far increased spatiotemporal resolution has led to active CMOS-based MEAs
within the last two decades. A certain portion of these approaches also has been commercialized since mid of the last decade.
In this talk, we will consider extracellular, i.e. non-invasive, recording and stimulation techniques, various design philosophies of high density CMOS MEAs, and CMOS integration issues with respect to interfacing materials. Circuit and system design aspects will be discussed with emphasis on signal-to-noise issues.
RRAM – the eNVM technology of the future
Thomas Kern, Infineon, Tuesday 20.02.24 at 4 PM
Abstract:
With the change to highly advanced CMOS technologies the integration of reliable and robust NVM technologies (Floating gate and charge trapping) came to an end. This was the kick-off for new emerging technologies where RRAM, MRAM and PCRAM have been matured the most as of today. Among these technologies RRAM is the most attractive one considering manufacturing cost, market acceptance (radiation hardness and magnetic immunity) and availability at foundries. In this talk RRAM cell characteristics and associated challenges will be presented. As an example Design solutions for Data memory for automotive applications will be explained. Neuromorphic computing with RRAM is shortly discussed as well. The talk will be concluded with summary and outlook on RRAM future.
Full-Stack Platform Empowering the Development of High-Performance Acoustic MEMS Systems
Dr. Tingzhong Xu, Silicon Austria Labs, Villach, Tuesday 09.01.24 at 4 PM
Abstract:
This lecture will be based on the fundamentals of PMUT, introducing the design, fabrication, characterization of acoustic MEMS devices, and the full stack modelling platform including the front-end analog circuits. It will also delve into typical development cases, exploring the status and future prospects of acoustic MEMS devices.
Three decades of arc-free reproducible CDM-like ESD testing from VF-TLP to CC-TLPESD
Dr.-Ing. Horst Gieser, Fraunhofer-Institut EMFT, Tuesday 28.11.23 at 4 PM
Abstract:
Charged Device Model CDM represents today’s reality of electrostatic risk during highly automated assembly, test and heterointegration of microelectronic circuits. There was no doubt about the failure signatures mainly in gate oxides behind the protection, between supply nets or in charge pumps and the need to test for their robustness. About 30 years ago the discussion started how discharge events with ps-risetimes and sub-nanosecond duration can be generated and captured with high fidelity and reproducibility and standards were developed at ESD Association and JEDEC. Nevertheless reproducibility between test systems even at the same test site and even repeatability within a single system became a resource consuming nightmare. Reason were the constructions of the test systems, the inadequate metrology for true-ps-transients and last but not least the variability of the switching spark of the air discharge. Therefore, a European team has developed the first arc free method with only a single pin in the discharge path - the Capacitively Coupled Transmission Line Pulsing cc-TLP. A remotely generated ps-rise time impulse is injected via a single short contact needle into the capacitance of an IC in a package, on a wafer or even as a bare die. Few mm-short means low-inductive. The contact geometry reaches from tin ball size down to some 10 µm pad sizes with an option for less. The repeatability is improved from more than 20 % of air-CDM to less than 3 % even for very low stress voltages of less than 10 V that become critical for single-digit nm technologies and heterointergation of chiplets into multichip modules. Finally in 2022, after many publication of correlation data and test setups in use at major stake holders the cc-TLP method has made it into a standard document of the ESD Association. The talk gives an overview over a long lasting journey which certainly has not reached its final destination.
mmW PCB design – Another dimension and challenge to IC design
Holger Kuhnert, System Application Architect, NXP Semiconductors, Tuesday 14.11.23 at 4 PM
Abstract:
Mastering mmW PCB design is an enabling technology to facilitate Automotive Radar sensor module development. These sensor modules are at the core of Automotive Driver Assistance Systems. This presentation discusses a decomposition of a state-of-the-art FMCW Radar sensor into its main building blocks and discusses the challenges in designing the mmW PCB.
Self-sensing of piezoelectrically driven micropumps: theory and technology
Dr. Martin Richter, Fraunhofer-Institut EMFT, München, Tuesday 31.10.23 at 4 PM
no Description
Organ-on-a-chip Technologies: in vitro veritas?
Prof. Peter Ertl, TU Vienna, Tuesday 25.07.23 at 4 PM
Organ-on-a-chip systems contain living human cell cultures that are grown in a dynamic microenvironment under controlled physiological conditions. These microphysiological systems allow biological, chemical and physical manipulation and analysis of organotypic structures. The reliable establishment of human tissue structures on a common chip platform has shown the potential to reduce and replace animal testing in basic and applied research as well as industrial QC measures. Additionally, organ-on-a-chip systems are used to establish personalized disease models with the aim of providing clinical-relevant information from a patient’s own cells to provided targeted therapy options. In this presentation the current state-of-the-art and selected applications of organ-on-a-chip systems in precision medicine will be introduced.
ASIC development of the company Heidenhain in the business area of measuring devices
Mr Schindler from Haidenhain Hochschulbetreuung 18.7.2023. 16:00
No Description
Application for Wicked (Analog Design Optimization Software)
Aravid Radhakrishnan Nair Tuesday 20.06.23 at 4 pm
Description available soon
Robust ultra low power hibernation mode & 28nm embedded RRAM for consumer and industrial products: Design and Reliability
Christoph Saas & Jan Otterstedt Tuesday 23.05.23 at 16:00
Both are topics from the Smarcard area
Integration technologies for sensors and IC on flexible film substrates
Landesberger Christof Tuesday 15.11.22 at 17:00
Technologies for assembly and interconnection of bare IC on flexible film substrates will be explained. Results from former research work at Fraunhofer EMFT on the mechanical stability of ultra-thin silicon chips (down to 12 µm thickness) on polyimide film substrates will be shown. Some application examples for thin and flexible electronics are presented as well.
Trends and Challenges of Advanced CMOS Technologies for Analog and High Frequency Applications
Peter Baumgartner Tuesday 17.1.23 at 17:00
The ongoing miniaturization of CMOS technologies is enabled by a variety of device and process innovations (e.g. FinFET transistors). Digital applications are driving this.
Advantages and challenges of these CMOS technologies for analog, high frequency and mmW applications will be considered in this talk.
Precision measurements in new generation of high power energy conversion systems
Misha Ivanov Tuesday 31.1.23 at 17:00
Energy revolution is on-going in our society and we increasingly use high voltage and high power converter systems in many areas of our lives. The renewable energy generators, electrical vehicles and their chargers, motor drives and similar devices routinely handle voltages between 800V and 2000 and currents up to 1000A. To ensure this equipment’s high efficiency and safety, the voltages and currents must be very accurately measured for many purposes: to control the switching of power SiC, GaN or IGBT transistors, to precisely measure the amount of charge in the battery or for billing, and to detect slightest defects in insulation that may endanger the user. We will discuss the precision sensors, amplifiers and ADCs that are needed to measure the needed high currents and high voltages accurately and without losses.
Introduction to Switching DC/DC Converters, Design Challenges and Opportunities
Puneet Sareen Tuesday 14.2.23 at 17:00
DC-DC converters are essential aspect of power electronics. Its voltage altering capabilities are used for power conversion applications. As the demand for different output voltage levels increases, so does the demand for new converter topologies, which can match the said demands in terms of performance and conversion efficiencies. DC-DC converters are widely used to efficiently produce a regulated voltage from a source that may or may not be well controlled to a load that may or may not be constant. A switched-mode DC/DC converts by storing the input energy periodically and then releasing that energy to the output at a different voltage. The storage can be in either a magnetic field component like an inductor or a transformer, or in an electric field component such as a capacitor. Output Voltage can also be lower or higher than the input voltage. This lecture briefly introduces DC-DC converters, common topologies, discusses important parameters and applications of DC-DC converters, design challenges, performance tradeoffs and design tricks.
Modelling and design of Interface circuit for hybrid energy harvesters
Ankesh Jain - Tuesday 7.6.22 at 17:00
This work presents the system level modelling of a hybrid energy harvesting device incorporating piezoelectric and electromagnetic transducers in order to optimize its output performance. The designed circuits are simulated for CMOS 180 nm process and the peak improvement obtained using the proposed technique is more than 1.3 times of the combined power when harvested individually.
CMOS Integrated Sensors and Sensor-Interfaces
Matthias Völker - Tuesday 21.06.22 at 17:00
Introduction into the work of the department for integrated sensor systems at the Fraunhofer IIS, Erlangen. Covering the range from CMOS integrated sensor elements over sensor interface circuits and important building blocks towards whole sensor systems on a chip.
Innovation in the field of ESD and its importance for integrated circuits
Harald Gossner - Tuesday 5.7.22 at 17:00
ESD is becoming more and more important as process nodes become smaller and smaller. In this lecture, new developments and their significance will be presented.
Design of High speed CTDSM
Ankesh Jain - Tuesday 19.7.22 at 17:00
Continuous-time Delta Sigma Modulators based on 1-bit quantizers with FIR feedback combine the advantages of single-bit and multibit operation. We propose the use of a duobinary test interface to extend the frequency range over which reliable laboratory measurements become possible. We show that using such an interface effectively randomizes the modulator output data and reduces high frequency content, thereby reducing the bandwidth demands made on the test equipment. It also reduces degradation of the modulator performance caused by package feed-through effects. Experimental results from a test chip in 90nm CMOS show that the proposed interface extends the upper sampling frequency limit of an existing single-bit CTDSM from 3.6 GHz to 4.4 GHz.
Characterization of High speed CTDSM
Ankesh Jain - Weddnesday 27.7.22 at 17:00
Continuous-time Delta Sigma Modulators based on 1-bit quantizers with FIR feedback combine the advantages of single-bit and multibit operation. We propose the use of a duobinary test interface to extend the frequency range over which reliable laboratory measurements become possible. We show that using such an interface effectively randomizes the modulator output data and reduces high frequency content, thereby reducing the bandwidth demands made on the test equipment. It also reduces degradation of the modulator performance caused by package feed-through effects. Experimental results from a test chip in 90nm CMOS show that the proposed interface extends the upper sampling frequency limit of an existing single-bit CTDSM from 3.6 GHz to 4.4 GHz.