Lectures by guest scientists and experts

Modelling and design of Interface circuit for hybrid energy harvesters

Ankesh Jain - Tuesday 7.6.22 at 17:00

This work presents the system level modelling of a hybrid energy harvesting device incorporating piezoelectric and electromagnetic transducers in order to optimize its output performance. The designed circuits are simulated for CMOS 180 nm process and the peak improvement obtained using the proposed technique is more than 1.3 times of the combined power when harvested individually.

 

CMOS Integrated Sensors and Sensor-Interfaces

Matthias Völker - Tuesday 21.06.22 at 17:00

Introduction into the work of the department for integrated sensor systems at the Fraunhofer IIS, Erlangen. Covering the range from CMOS integrated sensor elements over sensor interface circuits and important building blocks towards whole sensor systems on a chip.

 

Innovation in the field of ESD and its importance for integrated circuits

Harald Gossner - Tuesday 5.7.22 at 17:00

ESD is becoming more and more important as process nodes become smaller and smaller. In this lecture, new developments and their significance will be presented.

 

 

Design of High speed CTDSM

Ankesh Jain - Tuesday 19.7.22 at 17:00

Continuous-time Delta Sigma Modulators based on 1-bit quantizers with FIR feedback combine the advantages of single-bit and multibit operation. We propose the use of a duobinary test interface to extend the frequency range over which reliable laboratory measurements become possible. We show that using such an interface effectively randomizes the modulator output data and  reduces high frequency content, thereby reducing the bandwidth demands made on the test equipment. It also reduces degradation of the modulator performance caused by package feed-through effects.  Experimental results from a test chip in 90nm CMOS show that the proposed interface extends the upper sampling frequency limit of an existing  single-bit CTDSM from 3.6 GHz to 4.4 GHz.

 

Characterization of High speed CTDSM

Ankesh Jain - Weddnesday 27.7.22 at 17:00

Continuous-time Delta Sigma Modulators based on 1-bit quantizers with FIR feedback combine the advantages of single-bit and multibit operation. We propose the use of a duobinary test interface to extend the frequency range over which reliable laboratory measurements become possible. We show that using such an interface effectively randomizes the modulator output data and  reduces high frequency content, thereby reducing the bandwidth demands made on the test equipment. It also reduces degradation of the modulator performance caused by package feed-through effects.  Experimental results from a test chip in 90nm CMOS show that the proposed interface extends the upper sampling frequency limit of an existing  single-bit CTDSM from 3.6 GHz to 4.4 GHz.