Analog Workshop 2023

A Calibration-Free 96.7 dB SNDR 4 MS/s Continuous Time Incremental Sigma Delta Modulator With Single Feedback DAC

This presentation presents a calibration-free 96.7 dB SNDR 4 MS/s third order Continuous-Time Incremental Sigma-Delta modulator (CT I-SDM). The design relies on open-loop integrators leading to a capacitive input of 987 fF easing the design of driving stages. The performance is achieved through the use of a resistive multi bit feedback DAC employing a modified dynamic element matching scheme and supply current compensation to reduce distortion. Further, chopping is used to reduce the impact of flicker noise in the loop filter. The clock jitter requirements of the ADC are relaxed through the use of finite impulse response (FIR) feedback in combination with a 5 bit internal SAR ADC. The design is implemented in a 22 nm FDSOI technology consuming an area of 0.25 mm2.