Scientific Seminar Analog Chip Design
Lecturer (assistant) | |
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Number | 0000001693 |
Type | seminar |
Duration | 3 SWS |
Term | Wintersemester 2025/26 |
Language of instruction | English |
Position within curricula | See TUMonline |
Dates | See TUMonline |
- 13.10.2025 15:00-16:30 Online: Videokonferenz / Zoom etc.
- 16.01.2026 10:00-17:00 N3815, Seminarraum , Seminar Mikro- und Nanosystemtechnik und Seminar Analog Chip Design
- 19.01.2026 10:00-17:00 N3823, Seminarraum , Seminar Mikro- und Nanosystemtechnik und Seminar Analog Chip Design
Admission information
Description
Registration over Website and TUMonline.
https://www.ee.cit.tum.de/en/mnt/teaching/scientific-seminar-on-analog-chip-design/
https://www.ee.cit.tum.de/en/mnt/teaching/scientific-seminar-on-analog-chip-design/
Links
Important: Please register for the course in TUMonline, contact a supervisor for a topic and go to the introductory meeting. Afterwards you will receive a fixed place.
Current topics WS25/26
Name | Topic title | Topic description |
---|---|---|
Ruolan Jia | RHBD Techniques for D Flip-Flops: From SEU Mechanisms to Robust Circuit Implementations | In high-radiation environments, Single Event Upsets (SEUs) can flip bits in D flip-flops, causing data errors or system failures. Radiation Hardening by Design (RHBD) uses architectures like DICE, TMR, and Quatro to tolerate or correct SEUs at the circuit level.Each technique impacts area, power, and timing differently, requiring careful optimization for the target application. |
Nihal Deshpande | Effect of Traps on Noise in MOSFET devices | Traps are very important physical quantities in semiconductor devices that drastically affect the electrical performance of the device. They act similarly to dopings, supplying free carriers, enhancing recombination, and also affect the interface charges that reflect in the electrical behaviour. This survey aims to study traps, different types and positions, and their influence on the Noise performace in MOSFET devices. |
Nihal Deshpande | Thermal Network to model self-heating effect in MOSFET devices | Thermal networks exist to model self-heating effect in electronic devices that allows to find the localised heating and thermal behaviour of devices and circuits at large. This survey aims at understanding how the thermal networks model this behaviour, the different network topologies and methods that exist for thermal management, and their suitability for different applications. |
Nihal Deshpande | Mobility Models for MOSFETs: Model viability for room and cryogenic temperatures | There exists several mobility models for describing the carrier transport in channels for MOSFET devices. But these models are typically tuned and fitted for a narrow temperature range. When modelling devices at cryogenic temperatures, the contribution of phonon scattering and surface roughness scattering reduces, and coulomb scattering dominates. The TCAD models used in different TCAD software like Sentaurus use different models that model these contributions. In this survey, a review is made of the mobility models used in SPICE compact models like BSIM-BULK, TCAD models to study their viability at standard operating temperatures and at cryogenic temperatures. |
Ting-Li Hsu | Survey on Integrated RF Frontend Co-Design | Conntecting Transimitter/T-R Switch/Receiver on PCB with off-chip components introduces loss and cost in area occupation. Hence, co-design of LNA/PA/T-R Switch starts to catch researchers' attention for a more compact solution. In this seminar, the student is encouraged to investigate the methodology and topology to realize the co-design of RF frontends. |
Running Guo | Computing in Memory (CIM) using RRAM for AI application | Analog CIM using RRAM, digital CIM using RRAM, DRAM or SRAM, do a summary and comparison |
Damian Panter | Survey on Ultra-Low Power Clock References | Since most wearable electronic devices are battery-powered, one development goal for integrated circuits is ultra-low power consumption to extend battery-life and potentially support always-on operation. Clock references are among the essential circuits that are required not only for digital but also analog circuitry. In this study, several techniques and state-of-the-art implementations of clock references shall be investigated, which oscillate in the range of tens to hundreds of kHz. |
Himadri Shekhar Bhattacharyya | Survey on Charge Sampling PLL techniques for cryogenic temperatures (4K) | A very common method of voltage Sampling at generally done using TG switch or bootsrapping switches. For applications at 4K temperature TG switch has significant drawback. Because of threshold increase, there is not enough VGS for the switch to ON and OFF correctly. Also Ron increase near mid VDD range increases by an order of 3 to 4. This Survey includes a survey of possible charge sampling techniques which includes no TG switch overbridging the voltage sampling drawbacks. |
Himadri Shekhar Bhattacharyya | Literature Review on IQ generation Techniques for PLL | PLL VCO gives single phase frequency generation unless we use a quadrature VCO. This topic includes other possible techniques to investigate (for example DLL, Phase Interpolator) to generate IQ phase |
Zerbane Abderahim | Literature Review on Frequency Multiplier Chains in J-Band (220GHz - 325 GHz) | Signal Generation in J-Band is primaly done with a VCO at lower frequencies followed by multiplier chains. The task is to review the literature and compare all architectures in terms of outputpower, bandwidth, harmonic content, conversion gain, power consumption, phase noise and chip size. |
Kosmas Wernhard | RF Chiplet Interposer: Silicon vs Glass | Silicon interposers are the state of the art for connecting multiple chiplets, especially for digital designs. Glass interposers seem to offer multiple advantages over Si interposers, especially for RF applications. For the seminar, a comparison between Glass and Si interposers should be carried out with a focus on transmission line loss, antenna on interposer design, linearity, thermal behaviour, and design constraints. |
Ellen Merkel | Survey on ESD on-chip monitors | In today's rapidly evolving electronics landscape, the miniaturization of components and the increasing complexity of integrated circuits have made electronic devices more susceptible to electrostatic discharge (ESD) events. As we move toward advanced packaging techniques, such as 3D packaging and system-in-package (SiP) designs, the risk of ESD-related failures increases, and the detection of ESD in such complex production environments becomes much more challenging. One method of detecting ESD is by using on-chip ESD monitors. This paper should discuss various on-chip ESD monitors proposed in the literature, as well as their advantages and limitations. |