Lab CMOS PLL Circuit and System Design
| Vortragende/r (Mitwirkende/r) | |
|---|---|
| Nummer | 0000000812 |
| Art | Praktikum |
| Umfang | 5 SWS |
| Semester | Sommersemester 2026 |
| Unterrichtssprache | Deutsch,English |
| Stellung in Studienplänen | Siehe TUMonline |
| Termine | Siehe TUMonline |
- 22.07.2026 09:00-12:00 N1812, Seminar
- 22.07.2026 09:30-11:30 N1812, Seminar , Final Presentation
Teilnahmekriterien
Beschreibung
1. Analysis the PLL system and choose certion PLL topology with given specifications.
2. Model the PLL system with Matlab or LTspice.
3. Learn the CMOS circuit design knowledge from the prior basic lab (voltage reference, power supply, A/D and D/A).
4. Design a qualified PLL circuit and system with Cadence.
5. Simulate the PLL and extract its performances for circuit functionality, system stability and jitter.
6. Evaluate the non-idealities effects.
2. Model the PLL system with Matlab or LTspice.
3. Learn the CMOS circuit design knowledge from the prior basic lab (voltage reference, power supply, A/D and D/A).
4. Design a qualified PLL circuit and system with Cadence.
5. Simulate the PLL and extract its performances for circuit functionality, system stability and jitter.
6. Evaluate the non-idealities effects.
Inhaltliche Voraussetzungen
Solid-State and Semiconductor Device Physics, Analog and Mixed-Signal Electronics, Phase Locked Loop/Clocked Circuits